The present invention relates to a semiconductor device and, more particularly, to a semiconductor integrated circuit with a high integration density, which has a circuit for generating a d.c. reference voltage.
The higher the integration density of a semiconductor circuit device, the smaller are the elements of the circuit device. The sizes of the circuit elements are now at submicron level. In order to mount as many submicron-elements as possible on a chip substrate, the chip substrate needs to be large. However, the width of the chip substrate cannot be increased because of the limitations imposed on the packaging sizes of semiconductor devices. Therefore, the chip substrate is elongated. For example, the chip substrate of a 4-megabit dynamic random-access memory (DRAM), which has recently been developed, has a width of 6.9 mm and a length of 16.11 mm. This substrate is, so to speak, slim; its length is about 2.3 times its width.
The longer the chip substrate, the longer the inner wiring lines extending in the lengthwise direction of the substrate. When a great number of these wiring lines are used, they must be fine and juxtaposed at short intervals. As a result, the parasitic capacitances, such as the stray capacitance among these lines and the coupling capacitance between the substrate and these lines, are undesirably increased. Consequently, the internal impedance of the semiconductor circuit device increases, inevitably degrading the operating characteristics of the semiconductor circuit device.
Semiconductor DRAMS are known which have a circuit for generating a reference d.c. voltage for row- and column-address buffer circuits. To these DRAMs the above-mentioned phenomenon represents a very serious problem. This is because, in these DRAMs, an increase in the internal impedance directly reduces the reliability of the data-access operation. The longer and finer the wiring lines for applying the reference d.c. voltage Vref to the row- and column-address buffer circuits, the more the coupling-capacitance ratio rc for the substrate and these voltage-applying lines will increase. As a result, the potential of the voltage-applying lines (i.e., the reference voltage Vref for the address buffer circuit) fluctuates considerably when the potential of the bit lines changes from ground potential Vss to power-supply voltage Vcc, or vice versa. This large potential-fluctuation of the lines adversely reduces the operating tolerance of the address buffer circuits which, consequently, are more likely to malfunction, with the result that data cannot be correctly written into, or correctly read out from, the DRAM.
The existing 1-metabit DRAM has, in addition to redundant wiring lines, 8192 bit lines, reference-voltage transmission lines for applying the reference d.c. voltage to the sense amplifiers used in the address buffer and the data-input buffer, power-supply lines, and grounding lines. (Each bit line has 128 memory cells are connected thereto.) The DRAM is divided-driven in such a manner that the memory cells of this DRAM are divided into several groups of cell arrays. When the DRAM is set in a data-accessing mode, only one selected group of cell arrays is enabled. The cell arrays of the selected group are therefore charged during a precharge period, and are discharged during an active period. The cell arrays of the non-selected groups remain inoperative, and power is saved during the data-access operation of the DRAM.
In the DRAM having the structure described above, the boostrap ratio rB between each bit line and the substrate is approximately 14%. Hence, when the ground potential Vss and the power-supply voltage are 0 volts and 5 volts, respectively, the fluctuation Vsub of the substrate potential .DELTA.Vsub, which occurs as the potential of each bit line changes from the ground potential Vss to the power-supply voltage Vcc, or vice versa, can be given as: EQU .DELTA.Vsub=(Vcc-Vss).multidot.rB=.+-.0.7 (V) (1)
The coupling-capacitance ratio rc between the substrate, on the one hand, and the reference voltage-applying lines, on the other, will increase to as much as 0.58 when the width of the wiring lines is reduced, more wiring lines are used, and the wiring lines are juxtaposed at shorter intervals. When the substrate potential Vsub changes within the range of .+-.0.7 volts, the fluctuation .DELTA.Vref of the potential of the voltage-applying lines will be: EQU .DELTA.Vref =.DELTA.Vsub .multidot.rc=.+-.0.41(V) (2)
When the reference d.c. voltage Vref is 1.6 volts, this voltage will change considerably within the range of 1.19 to 2.01 volts as the potential of any bit line changes from the ground potential Vss to the power-supply voltage Vcc, or vice versa, due to the discharging of the bit line during the active-mode operation of the DRAM, or due to the charging of the bit line during the precharge-mode operation of the DRAM. When the reference potential Vref fluctuates as much as this, the margin for the logical-level discrimination within the address buffer circuit will greatly diminish, despite the fact that the range of the logical "HIGH" and "LOW" levels of the externally input address signals is fixed. In the worst case, this margin is nil. Hence, there is a strong possibility that both the row-address buffer circuit and the column-address buffer circuit will operate erroneously. In such circumstances, it is unlikely that a correct data-access operation can be achieved in the DRAM.